In this paper we propose a complete chain for synthesizing controllers from high-level specifications. From real-time properties expressed in the logic MTL we generate, under boun...
This paper presents a discrete-event approach to synthesis of transcription control for a class of (computational) gene networks. Given a set of genes and protein-gene and/or prote...
Highly regular, nanodevice based architectures have been proposed to replace pure CMOS based architectures in the emerging post CMOS era. Since bottom-up self-assembly is used to ...
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
A methodology for the synthesis of partially selfchecking multilevel logic circuits with low-cost paritybased concurrent error detection (CED) is described. A subset of the inputs...
Kartik Mohanram, Egor S. Sogomonyan, Michael G&oum...