564 search results - page 36 / 113 » Wireplanning in logic synthesis |
CAV
2007
Springer
14 years 2 months ago
2007
Springer
In this paper we propose a complete chain for synthesizing controllers from high-level specifications. From real-time properties expressed in the logic MTL we generate, under boun...
JCB
2006
13 years 8 months ago
2006
This paper presents a discrete-event approach to synthesis of transcription control for a class of (computational) gene networks. Given a set of genes and protein-gene and/or prote...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Highly regular, nanodevice based architectures have been proposed to replace pure CMOS based architectures in the emerging post CMOS era. Since bottom-up self-assembly is used to ...
TCAD
2008
13 years 8 months ago
2008
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
IOLTS
2003
IEEE
14 years 1 months ago
2003
IEEE
A methodology for the synthesis of partially selfchecking multilevel logic circuits with low-cost paritybased concurrent error detection (CED) is described. A subset of the inputs...