564 search results - page 47 / 113 » Wireplanning in logic synthesis |
ATVA
2006
Springer
14 years 7 days ago
2006
Springer
In synthesis we construct finite state systems from temporal specifications. While this problem is well understood in the classical setting of non-probabilistic synthesis, this pap...
FSTTCS
2007
Springer
14 years 2 months ago
2007
Springer
We examine a bidirectional Propositional Dynamic Logic (PDL) for message sequence charts (MSCs) extending LTL and TLC− . Every formula is translated into an equivalent communicat...
ICCAD
1997
IEEE
14 years 21 days ago
1997
IEEE
In this paper we present an algorithm for converting a BDD representation of a logic function into a multiple-level netlist of disjoint-support subfunctions. On the theoretical si...
CMSB
2006
Springer
14 years 6 days ago
2006
Springer
Based on the logical description of gene regulatory networks developed by R. Thomas, we introduce an enhanced modelling approach that uses timed automata. It yields a refined quali...
ASPDAC
2001
ACM
14 years 4 days ago
2001
ACM
Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Le...