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» Wireplanning in logic synthesis
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FCCM
2002
IEEE
146views VLSI» more  FCCM 2002»
14 years 2 months ago
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems
Several projects have developed compiler tools that translate high-level languages down to hardware description languages for mapping onto FPGAbased reconfigurable computers. Thes...
Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker...
ISSS
2002
IEEE
103views Hardware» more  ISSS 2002»
14 years 2 months ago
A Symbolic Approach for the Combined Solution of Scheduling and Allocation
Scheduling is widely recognized as a very important step in highlevel synthesis. Nevertheless, it is usually done without taking into account the effects on the actual hardware im...
Luciano Lavagno, Mihai T. Lazarescu, Stefano Quer,...
ICCAD
1995
IEEE
97views Hardware» more  ICCAD 1995»
14 years 1 months ago
Interface co-synthesis techniques for embedded systems
A key aspect of the synthesis of embedded systems is the automatic integration of system components. This entails the derivation of both the hardware and software interfaces that ...
Pai H. Chou, Ross B. Ortega, Gaetano Borriello
ICCAD
2007
IEEE
102views Hardware» more  ICCAD 2007»
14 years 6 months ago
Scalable exploration of functional dependency by interpolation and incremental SAT solving
Functional dependency is concerned with rewriting a Boolean function f as a function h over a set of base functions {g1, …, gn}, i.e. f = h(g1, …, gn). It plays an important r...
Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang H...
DAC
2010
ACM
14 years 1 months ago
Reducing the number of lines in reversible circuits
Reversible logic became a promising alternative to traditional circuits because of its applications e.g. in low-power design and quantum computation. As a result, design of revers...
Robert Wille, Mathias Soeken, Rolf Drechsler