564 search results - page 81 / 113 » Wireplanning in logic synthesis |
ISCAS
2003
IEEE
14 years 21 days ago
2003
IEEE
Ordered Binary Decision Diagrams (BDDs) are frequently used in logic synthesis. In this paper a new exact BDD minimization algorithm is presented, which is based on state space se...
ISVLSI
2002
IEEE
14 years 10 days ago
2002
IEEE
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...
DFT
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a system to evaluate the testability of an on-line testable circuit. The system operates at the RT-level, before the logic synthesis step, and allows for an ex...
VTS
1998
IEEE
13 years 11 months ago
1998
IEEE
A fast fault-tolerant controller structure is presented, which is capable of recovering from transient faults by performing a rollback operation in hardware. The proposed fault-to...
SP
2000
IEEE
13 years 11 months ago
2000
IEEE
Tradeoffs are an important part of engineering security. Protocol security is important. So are efficiency and cost. This paper provides an early framework for handling such aspec...