564 search results - page 95 / 113 » Wireplanning in logic synthesis |
DAC
1994
ACM
13 years 11 months ago
1994
ACM
In this paper, we revisit the classical problem of functional decomposition [1, 2] that arises so often in logic synthesis. One basic problem that has remained largely unaddressed...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
SAT sweeping is a method for simplifying an AND/INVERTER graph (AIG) by systematically merging graph vertices from the inputs towards the outputs using a combination of structural...
POPL
2004
ACM
14 years 7 months ago
2004
ACM
In prior work we introduced a pure type assignment system that encompasses a rich set of property types, including intersections, unions, and universally and existentially quantif...
DDECS
2008
IEEE
14 years 1 months ago
2008
IEEE
: We propose a simple and fast two-level minimization algorithm for completely specified functions in this paper. The algorithm is based on processing ternary trees. A ternary tree...
FPGA
2007
ACM
14 years 1 months ago
2007
ACM
We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-...