85 search results - page 8 / 17 » Wiring edge-disjoint layouts |
ISPD
2003
ACM
14 years 26 days ago
2003
ACM
Floorplanning individual pipelined array modules of a larger overall die can yield beneficial results. Critical paths in every pipeline stage of a pipelined design are roughly equ...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Wirelength estimation techniques typically contain a site density function that enumerates all possible path sites for each wirelength in an architecture and an occupation probabil...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
1In this paper, we will present an effective layout method for analog circuits. We consider symmetry constraint, common centroid constraint, device merging and device clustering du...
ITC
2003
IEEE
14 years 27 days ago
2003
IEEE
We present an efficient algorithm for identification of two-line bridges in combinational CMOS logic that narrows down the two-line bridge candidates based on tester responses for...
ARITH
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we explore the relationship between adder topology and energy efficiency. We compare the energy-delay tradeoff curves of selected 32-bit adder topologies, to determi...