85 search results - page 9 / 17 » Wiring edge-disjoint layouts |
ASPDAC
2005
ACM
13 years 9 months ago
2005
ACM
The synthesis of clock network in the presence of process variation is becoming a vital design issue towards the performance of digital circuits. In this paper, we propose a clock ...
DATE
2003
IEEE
14 years 28 days ago
2003
IEEE
We present a physical imrplementation of a 32-ports SPIN micro-network. For a 0.13 micron CMOS process, the total area is 4.6 ¢£¢¥¤ , for a cumulated bandwidth of about 100 G...
DAC
1998
ACM
13 years 12 months ago
1998
ACM
—Due to the scaling down of device geometry and increasing of frequency in deep submicron designs, crosstalk between interconnection wires has become an important issue in very l...
WSC
2008
13 years 10 months ago
2008
Visualization of individual network events is a crucial part of testing new network designs and analyzing network performance and efficiency. This research designed and developed ...
SLIP
2006
ACM
14 years 1 months ago
2006
ACM
A fundamental difference between ASICs and FPGAs is that wires in ASICs are designed such that it matches the requirements of a particular design. Wire parameters such as: length...