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15 years 8 months ago
Within-die Process Variations: How Accurately can They Be Statistically Modeled?
Within-die process variations arise during integrated circuit (IC) fabrication in the sub-100nm regime. These variations are of paramount concern as they deviate the performance of...
Brendan Hargreaves, Henrik Hult, Sherief Reda
ICCAD
2003
IEEE
205views Hardware» more  ICCAD 2003»
14 years 1 months ago
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
Aseem Agarwal, David Blaauw, Vladimir Zolotov
ICML
2004
IEEE
14 years 9 months ago
Variational methods for the Dirichlet process
Variational inference methods, including mean field methods and loopy belief propagation, have been widely used for approximate probabilistic inference in graphical models. While ...
David M. Blei, Michael I. Jordan
ICCAD
2004
IEEE
147views Hardware» more  ICCAD 2004»
14 years 5 months ago
Interval-valued reduced order statistical interconnect modeling
9, IO]. However, unlike the case with static timing, it is not so easy We show how recent advances in the handling of correlated interval representations of range uncertainty can b...
James D. Ma, Rob A. Rutenbar
ASPDAC
2009
ACM
161views Hardware» more  ASPDAC 2009»
14 years 3 months ago
Risk aversion min-period retiming under process variations
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
Jia Wang, Hai Zhou