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DAC
2006
ACM
14 years 8 months ago
A real time budgeting method for module-level-pipelined bus based system using bus scenarios
In designing bus based systems with parallel and pipelined architecture, it is important to derive a real time budget (a specified execution time limit) for each task of a bus bas...
Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Te...
MEMOCODE
2006
IEEE
14 years 1 months ago
A scenario-aware data flow model for combined long-run average and worst-case performance analysis
Data flow models are used for specifying and analysing signal processing and streaming applications. However, traditional data flow models are either not capable of expressing t...
Bart D. Theelen, Marc Geilen, Twan Basten, Jeroen ...
DAC
2006
ACM
14 years 1 months ago
Buffer memory optimization for video codec application modeled in Simulink
Reduction of the on-chip memory size is a key issue in video codec system design. Because video codec applications involve complex algorithms that are both data-intensive and cont...
Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Ami...
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
13 years 11 months ago
A Scalable Front-End Architecture for Fast Instruction Delivery
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
Glenn Reinman, Todd M. Austin, Brad Calder
IISWC
2006
IEEE
14 years 1 months ago
Characterization of Error-Tolerant Applications when Protecting Control Data
Soft errors have become a significant concern and recent studies have measured the “architectural vulnerability factor” of systems to such errors, or conversely, the potentia...
Darshan D. Thaker, Diana Franklin, John Oliver, Su...