85 search results - page 7 / 17 » Wrong-path Instruction Prefetching |
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
IPPS
2003
IEEE
14 years 22 days ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
—L1 instruction-cache misses pose a critical performance bottleneck in commercial server workloads. Cache access latency constraints preclude L1 instruction caches large enough t...
ISCA
1995
IEEE
13 years 11 months ago
1995
IEEE
Current trends in processor design are pointing to deeper and wider pipelines and superscalar architectures. The efficient use of these resources requires speculative execution, ...
CC
2007
Springer
14 years 1 months ago
2007
Springer
Reference counting is a classical garbage collection method. Recently, a series of papers have extended the basic method to drastically reduce its notorious overhead and extend the...