399 search results - page 38 / 80 » XTR Implementation on Reconfigurable Hardware |
ICASSP
2011
IEEE
13 years 7 days ago
2011
IEEE
Decoder architectures for architecture-aware Raptor codes having regular message access-and-processing patterns are presented. Raptor codes are a class of concatenated codes compo...
FPL
2006
Springer
14 years 4 days ago
2006
Springer
This paper presents FPGA implementations of the DES and Triple-DES with improved security against power analysis attacks. The proposed designs use Boolean masking, a previously in...
ISCAS
2008
IEEE
14 years 2 months ago
2008
IEEE
— This paper presents an analogue integrated circuit implementation of a cortical neuron model. The VLSI chip prototype has been implemented in a 0.35 µm CMOS technology. The si...
FPL
2005
Springer
14 years 2 months ago
2005
Springer
In this paper, we consider scanning and analyzing packets in order to detect hazardous contents using pattern matching. We introduce a hardware perfect-hashing technique to access...
CF
2006
ACM
14 years 2 months ago
2006
ACM
In this paper, we present a nano-scale reconfigurable mesh that is interconnected with ferromagnetic spin-wave buses. The architecture described here, while requiring the same num...