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» XTR Implementation on Reconfigurable Hardware
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DATE
2006
IEEE
88views Hardware» more  DATE 2006»
14 years 3 months ago
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
Paulo Sérgio B. do Nascimento, Manoel Euseb...
FCCM
2005
IEEE
115views VLSI» more  FCCM 2005»
14 years 3 months ago
FIFO Communication Models in Operating Systems for Reconfigurable Computing
Increasing demands upon embedded systems for higher level services like networking, user interfaces and file system management, are driving growth in fully-featured operating syst...
John A. Williams, Neil W. Bergmann, X. Xie
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
14 years 1 months ago
Power-aware mapping for reconfigurable NoC architectures
A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traff...
Mehdi Modarressi, Hamid Sarbazi-Azad
FPL
2000
Springer
96views Hardware» more  FPL 2000»
14 years 1 months ago
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures
Coarse-grain reconfigurable architectures have been a matter of intense research in the last few years. They promise to be more adequate for computational tasks due to their better...
Reiner W. Hartenstein, Michael Herz, Thomas Hoffma...
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
13 years 11 months ago
Reconfigurable Shuffle Network Design in LDPC Decoders
Several semi-parallel decoding architectures have been explored by researchers for the quasi-cyclic low density parity check (LDPC) codes. In these architectures, the reconfigurab...
Jun Tang, Tejas Bhatt, Vishwas Sundaramurthy