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FCCM
2008
IEEE
160views VLSI» more  FCCM 2008»
14 years 4 months ago
Facilitating Processor-Based DPR Systems for non-DPR Experts
Currently, only Xilinx Field Programmable Gate Arrays (FPGAs) support Dynamic Partial Reconfiguration (DPR). While there is currently some Computer Aided Design (CAD) tool support...
Edward Chen, William A. Gruver, Dorian Sabaz, Lesl...
ICIP
1995
IEEE
14 years 11 months ago
Parallel programmable video co-processor design
Modern video applications call for computationally intensive data processing at very high data rate. In order to meet the high-performance/low-cost constraints, the stateof-the-ar...
An-Yeu Wu, K. J. Ray Liu, Arun Raghupathy, Shang-C...
OSDI
2008
ACM
14 years 10 months ago
Block Mason
The flexibility provided by hardware virtualization allows administrators to rapidly create, destroy, and migrate systems across physical hosts. Unfortunately, the storage systems...
Dutch T. Meyer, Brendan Cully, Jake Wires, Norman ...
ISCAS
2007
IEEE
84views Hardware» more  ISCAS 2007»
14 years 4 months ago
High Speed 1-bit Bypass Adder Design for Low Precision Additions
—In this paper, we propose a high speed adder which is adopted for our reconfigurable architecture called FleXilicon. To support sub-word parallelism, the FleXilicon architecture...
Jong-Suk Lee, Dong Sam Ha
CODES
2005
IEEE
14 years 3 months ago
FlexPath NP: a network processor concept with application-driven flexible processing paths
In this paper, we present a new architectural concept for network processors called FlexPath NP. The central idea behind FlexPath NP is to systematically map network processor (NP...
Rainer Ohlendorf, Andreas Herkersdorf, Thomas Wild