35 search results - page 4 / 7 » Yield modelling and Yield Enhancement for FPGAs using Fault ... |
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
— As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to ...
ISCA
2010
IEEE
14 years 21 days ago
2010
IEEE
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
DAC
2010
ACM
13 years 6 months ago
2010
ACM
A three-dimensional (3D) CMOS imager constructed by stacking a pixel array of backside illuminated sensors, an analog-to-digital converter (ADC) array, and an image signal process...
DFT
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
DFT
2005
IEEE
14 years 1 months ago
2005
IEEE
We propose a novel system-level error tolerance approach specifically targeted for multimedia compression algorithms. In particular we focus on the motion estimation process perf...