1000 search results - page 172 / 200 » Yield-Aware Cache Architectures |
DAC
2000
ACM
14 years 8 months ago
2000
ACM
erse approaches at all levels of abstraction starting from the physical level up to the system level. Experience shows that a highlevel method may have a larger impact since the de...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
Hardware transactional memory should support unbounded transactions: transactions of arbitrary size and duration. We describe a hardware implementation of unbounded transactional ...
UM
2009
Springer
14 years 2 months ago
2009
Springer
Abstract. Reconciling personalization with privacy has been a continuing interest in the user modeling community. In prior work, we proposed a dynamic privacy-enhancing user modeli...
IPCCC
2007
IEEE
14 years 2 months ago
2007
IEEE
As Chip Multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors to the PC market. In this paper, perfor...
ICS
2007
Tsinghua U.
14 years 1 months ago
2007
Tsinghua U.
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...