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HPCA
2009
IEEE
14 years 8 months ago
Dacota: Post-silicon validation of the memory subsystem in multi-core designs
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
Andrew DeOrio, Ilya Wagner, Valeria Bertacco
HPCA
2003
IEEE
14 years 8 months ago
TCP: Tag Correlating Prefetchers
Although caches for decades have been the backbone of the memory system, the speed gap between CPU and main memory suggests their augmentation with prefetching mechanisms. Recentl...
Zhigang Hu, Margaret Martonosi, Stefanos Kaxiras
HPCA
2003
IEEE
14 years 8 months ago
Memory System Behavior of Java-Based Middleware
Java-based middleware, and application servers in particular, are rapidly gaining importance as a new class of workload for commercial multiprocessor servers. SPEC has recognized ...
Martin Karlsson, Kevin E. Moore, Erik Hagersten, D...
CODES
2009
IEEE
14 years 2 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
HPDC
2008
IEEE
14 years 2 months ago
Combining batch execution and leasing using virtual machines
As cluster computers are used for a wider range of applications, we encounter the need to deliver resources at particular times, to meet particular deadlines, and/or at the same t...
Borja Sotomayor, Kate Keahey, Ian T. Foster