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HIPEAC
2010
Springer
13 years 9 months ago
Virtual Ways: Efficient Coherence for Architecturally Visible Storage in Automatic Instruction Set Extensions
Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include...
Theo Kluter, Samuel Burri, Philip Brisk, Edoardo C...
SIGMOD
1992
ACM
111views Database» more  SIGMOD 1992»
13 years 11 months ago
Performance Evaluation of Extended Storage Architectures for Transaction Processing
: The use of non-volatile semiconductor memory within an extended storage hierarchy promises significant performance improvements for transaction processing. Although page-addressa...
Erhard Rahm
MICRO
2010
IEEE
215views Hardware» more  MICRO 2010»
13 years 6 months ago
A Task-Centric Memory Model for Scalable Accelerator Architectures
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
John H. Kelm, Daniel R. Johnson, Steven S. Lumetta...
DAC
2010
ACM
13 years 8 months ago
Performance and power modeling in a multi-programmed multi-core environment
This paper describes a fast, automated technique for accurate on-line estimation of the performance and power consumption of interacting processes in a multi-programmed, multi-cor...
Xi Chen, Chi Xu, Robert P. Dick, Zhuoqing Morley M...
JCP
2007
181views more  JCP 2007»
13 years 7 months ago
Reducing Energy Consumption of Wireless Sensor Networks through Processor Optimizations
When the environmental conditions are stable, a typical Wireless Sensor Network (WSN) application may sense and process very similar or constant data values for long durations. Thi...
Gürhan Küçük, Can Basaran