1000 search results - page 28 / 200 » Yield-Aware Cache Architectures |
SIGMETRICS
1997
ACM
13 years 12 months ago
1997
ACM
In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel runnin...
EUROPAR
1997
Springer
13 years 12 months ago
1997
Springer
Instruction scheduling in general, and software pipelining in particular face the di cult task of scheduling operations in the presence of uncertain latencies. The largest contrib...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
HIPC
2009
Springer
13 years 5 months ago
2009
Springer
In many-core architectures, memory blocks are commonly assigned to the banks of a NUCA cache by following a physical mapping. This mapping assigns blocks to cache banks in a round-...
WIESS
2000
13 years 9 months ago
2000
The HP V-Class server family provides up to 32 processors and 32 GB of memory in a single cabinet. Scalable Computing Architecture technology allows multiple V-Class cabinets to b...