1000 search results - page 30 / 200 » Yield-Aware Cache Architectures |
ISLPED
2003
ACM
14 years 1 months ago
2003
ACM
A new architectural technique to reduce power dissipation in data caches is proposed. In multimedia applications, a major portion of data cache accesses hit in the same cache set ...
DATE
2011
IEEE
12 years 11 months ago
2011
IEEE
Current processors are optimized for average case performance, often leading to a high worst-case execution time (WCET). Many architectural features that increase the average case...
JSA
2008
13 years 7 months ago
2008
Architectural advancements in modern processor designs increase average performance with features such as pipelines, caches, branch prediction, and out-of-order execution. However...
DAC
2011
ACM
12 years 7 months ago
2011
ACM
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
NAA
2004
Springer
14 years 1 months ago
2004
Springer
In this paper, we develop a probabilistic model for estimation of the numbers of cache misses during the sparse matrix-vector multiplication (for both general and symmetric matrice...