1000 search results - page 39 / 200 » Yield-Aware Cache Architectures |
HPCA
1998
IEEE
14 years 18 hour ago
1998
IEEE
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and d...
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
DAGSTUHL
2007
13 years 9 months ago
2007
The model-based transformation of loop programs is a way of detecting fine-grained parallelism in sequential programs. One of the challenges is to agglomerate the parallelism to a...
ANCS
2009
ACM
13 years 5 months ago
2009
ACM
We propose MCRingBuffer, a lock-free, cache-efficient shared ring buffer that provides fast data accesses among threads running in multi-core architectures. MCRingBuffer seeks to ...