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SOCA
2010
IEEE
13 years 5 months ago
Exploiting multicores to optimize business process execution
While modern CPUs offer an increasing number of cores with shared caches, prevailing execution engines for business processes, workflows, or Web service compositions have not been ...
Achille Peternier, Daniele Bonetta, Cesare Pautass...
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
14 years 27 days ago
Data marshaling for multi-core architectures
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
M. Aater Suleman, Onur Mutlu, José A. Joao,...
SBACPAD
2006
IEEE
81views Hardware» more  SBACPAD 2006»
14 years 1 months ago
Scalable Value-Cache Based Compression Schemes for Multiprocessors
Martin Thuresson, Per Stenström
HPCA
2009
IEEE
14 years 8 months ago
Design and implementation of software-managed caches for multicores with local memory
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...
Sangmin Seo, Jaejin Lee, Zehra Sura
ICCD
2008
IEEE
118views Hardware» more  ICCD 2008»
14 years 4 months ago
Adaptive techniques for leakage power management in L2 cache peripheral circuits
— Recent studies indicate that a considerable amount of an L2 cache leakage power is dissipated in its peripheral circuits, e.g., decoders, word-lines and I/O drivers. In additio...
Houman Homayoun, Alexander V. Veidenbaum, Jean-Luc...