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APCCAS
2002
IEEE
100views Hardware» more  APCCAS 2002»
14 years 3 months ago
On three-dimensional layout of pyramid networks
The pyramid networks are well-known as suitable structures for parallel computations such as image processing. This paper shows a practical 3D VLSI layout of the N-vertex pyramid ...
T. Yamada, N. Fujii, S. Ueno
APCCAS
2002
IEEE
95views Hardware» more  APCCAS 2002»
14 years 3 months ago
Reducing power consumption of instruction ROMs by exploiting instruction frequency
This paper proposes a new approach to reducing the power consumption of instruction ROMs for embedded systems. The power consumption of instruction ROMs strongly depends on the sw...
Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami
APCCAS
2002
IEEE
157views Hardware» more  APCCAS 2002»
14 years 3 months ago
Multiplier energy reduction through bypassing of partial products
Designof portablebattery operatedmultimediadevices requires energy-ecient multiplication circuits. This paper presents a novel approach to reduce power consumption of digital mul...
Jun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue
APCCAS
2002
IEEE
92views Hardware» more  APCCAS 2002»
14 years 3 months ago
A cellular-automaton-type image extraction algorithm and its implementation using an FPGA
This paper proposes a new region extraction algorithm based on cellular automaton operation, which only utilizes the region boundary information of the image. A simple pixel circu...
Teppei Nakano, Takashi Morie, Makoto Nagata, Atsus...
APCCAS
2002
IEEE
156views Hardware» more  APCCAS 2002»
14 years 3 months ago
Bit-plane watermarking for zerotree-coded images
In this paper, we develop a robust bit-plane watermarking technique based on zerotree coding. A robust watermark is an imperceptible but indelible code that can be used for owners...
Shih-Hsuan Yang, Hsin-Chang Chen