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ASPDAC
2004
ACM
96views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Mixed-clock issue queue design for energy aware, high-performance cores
- Globally-Asynchronous, Locally-Synchronous (GALS) design style has started to gain interest recently as a possible solution to the increased design complexity, power and thermal ...
Venkata Syam P. Rapaka, Emil Talpes, Diana Marcule...
ASPDAC
2004
ACM
85views Hardware» more  ASPDAC 2004»
14 years 4 months ago
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance and signal integrity. Buffer insertion is one...
Yi-Hui Cheng, Yao-Wen Chang
ASPDAC
2004
ACM
97views Hardware» more  ASPDAC 2004»
14 years 4 months ago
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
Weiping Shi, Zhuo Li, Charles J. Alpert
ASPDAC
2004
ACM
151views Hardware» more  ASPDAC 2004»
14 years 4 months ago
Combinatorial group testing methods for the BIST diagnosis problem
— We examine an abstract formulation of BIST diagnosis in digital logic systems. The BIST diagnosis problem has applications that include identification of erroneous test vector...
Andrew B. Kahng, Sherief Reda
ASPDAC
2004
ACM
118views Hardware» more  ASPDAC 2004»
14 years 4 months ago
Fast and efficient voltage scheduling by evolutionary slack distribution
- To minimize energy consumption by voltage scaling in design of heterogeneousreal-time embeddedsystems, it is necessary to perfom two distinct tasks: task scheduling (TS) and volt...
Bita Gorjiara, Pai H. Chou, Nader Bagherzadeh, Meh...