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DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
14 years 2 months ago
Layout to Logic Defect Analysis for Hierarchical Test Generation
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A...
DAC
2007
ACM
14 years 9 months ago
PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels
Abstract-- The PPV is a robust phase domain macromodel for oscillators. It has been proven to predict oscillators' responses correctly under small signal perturbations, and ca...
Zhichun Wang, Xiaolue Lai, Jaijeet S. Roychowdhury
BIBE
2007
IEEE
126views Bioinformatics» more  BIBE 2007»
13 years 10 months ago
An End-to-End Process for Cancer Identification from Images of Lung Tissue
— This research describes a non-interactive process that applies several forms of computational intelligence to the task of classifying biopsy lung tissue samples based on visual...
Walker H. Land Jr., Daniel W. McKee, Tatyana Zhuko...
ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
14 years 17 days ago
Optimization of Arithmetic Datapaths with Finite Word-Length Operands
Abstract: This paper presents an approach to area optimization of arithmetic datapaths that perform polynomial computations over bit-vectors with finite widths. Examples of such de...
Sivaram Gopalakrishnan, Priyank Kalla, Florian Ene...
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
14 years 14 days ago
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops
he abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification m...
Tarvo Raudvere, Ingo Sander, Axel Jantsch