We propose an efficient hardware architecture for the Blowfish algorithm [1]. The speed is up to 4 bit/clock, which is 9 times faster than a Pentium. By applying operator-reschedul...
This paper presents a new compaction algorithm to improve the yield of IC layout. The yield is improved by reducing the area where the faults are more likely to happen known as cr...
We consider a new model for computing with uncertainty. It is desired to compute a function fX1; : : : ; Xn where X1; : : : ; Xn are unknown, but guaranteed to lie in speci ed i...
This paper presents a methodology for parallel and distributed simulation of VHDL using the PDES (parallel discrete-event simulation) paradigm. To achieve better features and perf...