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DATE
2002
IEEE
94views Hardware» more  DATE 2002»
14 years 2 months ago
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
Vivekananda M. Vedula, Jacob A. Abraham
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
14 years 2 months ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
14 years 2 months ago
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses
Due to the increasing operating frequencies and the manner in which the corresponding integrated circuits and systems must be designed, the extraction, modeling and simulation of ...
Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie...
DATE
2002
IEEE
123views Hardware» more  DATE 2002»
14 years 2 months ago
False Path Elimination in Quasi-Static Scheduling
We have developed a technique to compute a Quasi Static Schedule of a concurrent specification for the software partition of an embedded system. Previous work did not take into a...
G. Arrigoni, L. Duchini, Claudio Passerone, Lucian...
DATE
2002
IEEE
96views Hardware» more  DATE 2002»
14 years 2 months ago
A Linear-Centric Simulation Framework for Parametric Fluctuations
The relative tolerances for interconnect and device parameter variations have not scaled with feature sizes which have brought about significant performance variability. As we sca...
Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi