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84
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DDECS
2007
IEEE
80views Hardware» more  DDECS 2007»
15 years 10 months ago
New Strategies for System-Level Design
Daniel D. Gajski
103
Voted
DDECS
2007
IEEE
103views Hardware» more  DDECS 2007»
15 years 10 months ago
On Variable Selection in SAT-LP-based Bounded Model Checking of Linear Hybrid Automata
Marc Herbstritt, Bernd Becker, Erika Ábrah&...
128
Voted
DDECS
2007
IEEE
86views Hardware» more  DDECS 2007»
15 years 10 months ago
Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates
— This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detec...
Lukás Sekanina
123
Voted
DDECS
2007
IEEE
121views Hardware» more  DDECS 2007»
15 years 10 months ago
A Novel Parity Bit Scheme for SBox in AES Circuits
– This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only ...
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouze...
110
Voted
DDECS
2007
IEEE
80views Hardware» more  DDECS 2007»
15 years 10 months ago
Design Platform for Quick Integration of an Internet Connectivity into System-on-Chips
— The paper describes pre-integrated subsystem consisting of a configurable 8-bit microcontroller and an Internet connection solution. The latter integrates Ethernet Media Access...
Bartosz Wojciechowski, Tomasz Kowalczyk, Wojciech ...