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DDECS
2007
IEEE

Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates

14 years 6 months ago
Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates
— This paper describes a new self-testing 1-bit full adder. This circuit consists of three polymorphic NAND/NOR gates, two XOR gates and two inverters. The adder is able to detect a reasonable number of stuck-at-faults without the need of any additional logic and diagnostic signals. A fault is indicated by oscillations at the carry-out output. Properties of n-bit carrypropagate adder which is composed of the proposed 1-bit selftesting adders are investigated.
Lukás Sekanina
Added 02 Jun 2010
Updated 02 Jun 2010
Type Conference
Year 2007
Where DDECS
Authors Lukás Sekanina
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