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DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
We present the architecture of digit-serial normal basis multiplier over GF(2m ). The multiplier was derived from the multiplier of Agnew et al. Proposed multiplier is scalable by...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
Abstract. In an embedded multiprocessor system the minimum throughput and maximum latency of real-time applications are usually derived given the worst-case execution time of the s...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
Today energy is an important factor in designing a multiprocessor system. The overall goal of this work is to propose a methodology for design space exploration of VLIW multiproce...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
During synthesis of circuits for Boolean functions area, delay and testability are optimization goals that often contradict each other. Multi-level circuits are often quite small ...
DSD
2007
IEEE
14 years 1 months ago
2007
IEEE
Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability id...