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ET
2002
13 years 9 months ago
2002
We propose an integrated framework for the design of SOC test solutions, which includes a set of algorithms for early design space exploration as well as extensive optimization for...
ET
2002
13 years 9 months ago
2002
As we approach 100nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-onchips. Voltage distortion (noise) and delay viol...
ET
2002
13 years 9 months ago
2002
Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is prop...
ET
2002
13 years 9 months ago
2002
In this paper we explore two alternative approaches to system diagnosis. The first strategy is based on testability analysis performed by SATAN tool. The second approach performed ...
ET
2002
13 years 9 months ago
2002
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional co...