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IPCCC
2007
IEEE
14 years 5 months ago
Memory Performance and Scalability of Intel's and AMD's Dual-Core Processors: A Case Study
As Chip Multiprocessor (CMP) has become the mainstream in processor architectures, Intel and AMD have introduced their dual-core processors to the PC market. In this paper, perfor...
Lu Peng, Jih-Kwon Peir, Tribuvan K. Prakash, Yen-K...
ISCA
2007
IEEE
174views Hardware» more  ISCA 2007»
14 years 5 months ago
An integrated hardware-software approach to flexible transactional memory
There has been considerable recent interest in the support of transactional memory (TM) in both hardware and software. We present an intermediate approach, in which hardware is us...
Arrvindh Shriraman, Michael F. Spear, Hemayet Hoss...
ISCAS
2007
IEEE
92views Hardware» more  ISCAS 2007»
14 years 5 months ago
Macroblock-Level Adaptive Scan Scheme for Discrete Cosine Transform Coefficients
—Discrete Cosine Transform (DCT) has been widely used in image/video coding systems, where zigzag scan is usually employed for DCT coefficient organization. However, due to local...
Li Zhang, Wen Gao, Qiang Wang, Debin Zhao
ISQED
2007
IEEE
160views Hardware» more  ISQED 2007»
14 years 5 months ago
On-Chip Inductance in X Architecture Enabled Design
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
Santosh Shah, Arani Sinha, Li Song, Narain D. Aror...
CIVR
2007
Springer
273views Image Analysis» more  CIVR 2007»
14 years 5 months ago
Scalable near identical image and shot detection
This paper proposes and compares two novel schemes for near duplicate image and video-shot detection. The first approach is based on global hierarchical colour histograms, using ...
Ondrej Chum, James Philbin, Michael Isard, Andrew ...