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ACIVS
2006
Springer
14 years 21 days ago
Dedicated Hardware for Real-Time Computation of Second-Order Statistical Features for High Resolution Images
We present a novel dedicated hardware system for the extraction of second-order statistical features from high-resolution images. The selected features are based on gray level co-o...
Dimitris G. Bariamis, Dimitrios K. Iakovidis, Dimi...
INTEGRATION
2008
127views more  INTEGRATION 2008»
13 years 5 months ago
A Viterbi decoder architecture for a standard-agile and reprogrammable transceiver
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
Lucia Bissi, Pisana Placidi, Giuseppe Baruffa, And...
FPL
2006
Springer
96views Hardware» more  FPL 2006»
13 years 10 months ago
High Speed Document Clustering in Reconfigurable Hardware
High-performance document clustering systems enable similar documents to automatically self-organize into groups. In the past, the large amount of computational time needed to clu...
G. Adam Covington, Charles L. G. Comstock, Andrew ...
DATE
2007
IEEE
184views Hardware» more  DATE 2007»
14 years 1 months ago
New safety critical radio altimeter for airbus and related design flow
The latest generation of the ERT560 Digital Radio Altimeter (DRA) developed for the Airbus A380 is the result of Thales’ 40 years experience. Over 40,000 radio-altimeters have b...
D. Hairion, S. Emeriau, E. Combot, Michel Sarlotte
DATE
2000
IEEE
142views Hardware» more  DATE 2000»
13 years 11 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi