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FPGA
2003
ACM
138views FPGA» more  FPGA 2003»
14 years 3 months ago
Automatic transistor and physical design of FPGA tiles from an architectural specification
One of the most difficult and time-consuming steps in the creation of an FPGA is its transistor-level design and physical layout. Modern commercial FPGAs typically consume anywher...
Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron E...
FPGA
2003
ACM
123views FPGA» more  FPGA 2003»
14 years 3 months ago
Wire type assignment for FPGA routing
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
FPL
2003
Springer
109views Hardware» more  FPL 2003»
14 years 3 months ago
Globally Asynchronous Locally Synchronous FPGA Architectures
Abstract. Globally Asynchronous Locally Synchronous (GALS) Systems have provoked renewed interest over recent years as they have the potential to combine the benefits of asynchron...
Andrew Royal, Peter Y. K. Cheung
FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
14 years 3 months ago
Reducing pin and area overhead in fault-tolerant FPGA-based designs
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz...
EH
2003
IEEE
138views Hardware» more  EH 2003»
14 years 3 months ago
Implementing Evolution of FIR-Filters Efficiently in an FPGA
Reconfigurable hardware devices make it possible to change the topology of electronic circuits at runtime. Using reconfigurable devices as a platform for Evolvable hardware (EHW) ...
Knut Arne Vinger, Jim Torresen