FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped...
In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate...
In this paper, we propose a method for speeding-up applications by partitioning them between the reconfigurable hardware blocks of different granularity and mapping critical parts...
Michalis D. Galanis, Grigoris Dimitroulakos, Costa...
The solution to a set of sparse linear equations Ax = b, where A is an n×n sparse matrix and b is an n-element vector, can be obtained using the W-matrix method. An enhanced vect...
This paper presents a residential gateway (RG) prototyping process using Xilinx Integrated Software Environment (ISE) version 6.1i. The RG was designed for broadband residential m...