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FPL
2005
Springer
89views Hardware» more  FPL 2005»
14 years 4 months ago
Snow 2.0 IP Core for Trusted Hardware
Stream ciphers are a promising technique for encryption in trusted hardware. ISO/IEC standardization is currently under way and SNOW 2.0 is one of the remaining candidates. Its sof...
Wenhai Fang, Thomas Johansson, Lambert Spaanenburg
FPL
2005
Springer
100views Hardware» more  FPL 2005»
14 years 4 months ago
HAIL: A Hardware-Accelerated Algorithm for Language Identification
A hardware-accelerated algorithm has been designed to automatically identify the primary languages used in documents transferred over the Internet. The algorithm has been implemen...
Charles M. Kastner, G. Adam Covington, Andrew A. L...
FPL
2005
Springer
114views Hardware» more  FPL 2005»
14 years 4 months ago
Post-Placement BDD-Based Decomposition for FPGAs
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
Valavan Manohararajah, Deshanand P. Singh, Stephen...
FPL
2005
Springer
107views Hardware» more  FPL 2005»
14 years 4 months ago
Programmable Numerical Function Generators: Architectures and Synthesis Method
This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal,...
Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler
FPL
2005
Springer
100views Hardware» more  FPL 2005»
14 years 4 months ago
Power and Area Optimization for Multiple Restricted Multiplication
This paper presents a design and optimization technique for the Multiple Restricted Multiplication problem [1]. This refers to a situation where a single variable is multiplied by...
Nalin Sidahao, George A. Constantinides, Peter Y. ...