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FPL
2005
Springer
172views Hardware» more  FPL 2005»
14 years 3 months ago
An FPGA Network Architecture for Accelerating 3DES - CBC
This paper presents a DES/3DES core that will support Cipher Block Chaining (CBC) and also has a built in keygen that together take up about 10% of the resources in a Xilinx Virte...
Chin Mun Wee, Peter R. Sutton, Neil W. Bergmann
PREMI
2005
Springer
14 years 3 months ago
Artificial Neural Network Engine: Parallel and Parameterized Architecture Implemented in FPGA
In this paper we present and analyze an artificial neural network hardware engine, its architecture and implementation. The engine was designed to solve performance problems of the...
Milene Barbosa Carvalho, Alexandre Marques Amaral,...
DAC
2005
ACM
13 years 11 months ago
Multiplexer restructuring for FPGA implementation cost reduction
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
Paul Metzgen, Dominic Nancekievill
FPL
2005
Springer
96views Hardware» more  FPL 2005»
14 years 3 months ago
FPGA PLB Evaluation using Quantified Boolean Satisfiability
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
ASPDAC
2005
ACM
89views Hardware» more  ASPDAC 2005»
13 years 11 months ago
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...
Yan Lin, Fei Li, Lei He