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DAC
2006
ACM
14 years 9 months ago
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
Yu Hu, Yan Lin, Lei He, Tim Tuan
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
14 years 2 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
FPGA
2006
ACM
125views FPGA» more  FPGA 2006»
14 years 7 days ago
Armada: timing-driven pipeline-aware routing for FPGAs
While previous research has shown that FPGAs can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups ha...
Kenneth Eguro, Scott Hauck
FCCM
2006
IEEE
137views VLSI» more  FCCM 2006»
14 years 2 months ago
Single Pass, BLAST-Like, Approximate String Matching on FPGAs
Abstract: Approximate string matching is fundamental to bioinformatics, and has been the subject of numerous FPGA acceleration studies. We address issues with respect to FPGA imple...
Martin C. Herbordt, Josh Model, Yongfeng Gu, Bhara...
ARC
2006
Springer
135views Hardware» more  ARC 2006»
14 years 10 days ago
QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection
To fill the gap between increasing demand for reconfigurability and performance efficiency, CGRAs are seen to be an emerging platform. In this paper, a new architecture, QUKU, is d...
Sunil Shukla, Neil W. Bergmann, Jürgen Becker