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INTEGRATION
2008
13 years 7 months ago
2008
This paper presents a Viterbi Decoder (VD) architecture for a programmable data transmission system, implemented using a Field Programmable Gate Array (FPGA) device. This VD has b...
JUCS
2010
13 years 7 months ago
2010
: Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways...
IAJIT
2006
13 years 8 months ago
2006
In this paper, a fast hardware architecture for elliptic curve cryptography computation in Galois Field GF(p) is proposed. The architecture is implemented for 160-bits, as its dat...
FCCM
2006
IEEE
14 years 2 months ago
2006
IEEE
It has been shown that a small number of FPGAs can significantly accelerate certain computing tasks by up to two or three orders of magnitude. However, particularly intensive lar...
ISCAS
2006
IEEE
14 years 2 months ago
2006
IEEE
— We propose a fast Modular Arithmetic Logic Unit (MALU) that is scalable in the digit size (d) and the field size (k). The datapath of MALU has chains of Carry Save Adders (CSA...