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AHS
2006
IEEE
137views Hardware» more  AHS 2006»
14 years 2 months ago
Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
Wing On Fung, Tughrul Arslan, Sami Khawam
APCCAS
2006
IEEE
245views Hardware» more  APCCAS 2006»
14 years 2 months ago
Digital Audio Broadcasting System Modeling and Hardware Implementation
— DAB is a growing communication technology for digital audio broadcasting and demands higher concentration on flexible and cost optimum implementations for use in new mobile ele...
Nariman Moezzi Madani, Hamed Holisaz, Seid Mehdi F...
AVSS
2006
IEEE
14 years 2 months ago
Real-Time Video Segmentation with VGA Resolution and Memory Bandwidth Reduction
This paper presents the implementation of a video segmentation unit used for embedded automated video surveillance systems. Various aspects of the underlying segmentation algorith...
Hongtu Jiang, Viktor Öwall, Håkan Ard&o...
CCECE
2006
IEEE
14 years 2 months ago
Towards the System-on-Chip Realization of a Sensorless Vector Controller with Microsecond-order Computation Time
— The aim of this research is to implement sensorless vector control algorithms on a single, eventually reconfigurable, chip, with a computation timing constraint of, at most, 1...
Rachid Beguenane, Jean-Gabriel Mailloux, Sté...
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
14 years 2 months ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...