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GLVLSI
2007
IEEE
111views VLSI» more  GLVLSI 2007»
14 years 4 months ago
Probabilistic gate-level power estimation using a novel waveform set method
A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Ein...
GLVLSI
2007
IEEE
172views VLSI» more  GLVLSI 2007»
14 years 4 months ago
The effect of temperature on cache size tuning for low energy embedded systems
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in t...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
GLVLSI
2007
IEEE
106views VLSI» more  GLVLSI 2007»
14 years 4 months ago
Floorplan repair using dynamic whitespace management
We describe an efficient, top-down strategy for overlap removal and floorplan repair which repairs overlaps in floorplans produced by placement algorithms or rough floorplanni...
Kristofer Vorwerk, Andrew A. Kennings, Doris T. Ch...
GLVLSI
2007
IEEE
140views VLSI» more  GLVLSI 2007»
14 years 4 months ago
Structured and tuned array generation (STAG) for high-performance random logic
Regularly structured design techniques can combat complexity on a variety of fronts. We present the Structured and Tuned Array Generation (STAG) design methodology, which provides...
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kos...
GLVLSI
2007
IEEE
189views VLSI» more  GLVLSI 2007»
14 years 4 months ago
Hardware-accelerated path-delay fault grading of functional test programs for processor-based systems
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
Paolo Bernardi, Michelangelo Grosso, Matteo Sonza ...