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ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
13 years 11 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
ICCAD
1997
IEEE
97views Hardware» more  ICCAD 1997»
13 years 11 months ago
Low power logic synthesis for XOR based circuits
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
Unni Narayanan, C. L. Liu
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
13 years 11 months ago
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip memories. With the increasing gap between on-chip and off-chip memory access delays, it is...
Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nico...
ICCAD
1997
IEEE
117views Hardware» more  ICCAD 1997»
13 years 11 months ago
Generalized matching from theory to application
This paper presents a novel approach for post-mapping optimization. We exploit the concept of generalized matching, a technique that nds symbolically all possible matching assignm...
Patrick Vuillod, Luca Benini, Giovanni De Micheli
ICCAD
1997
IEEE
121views Hardware» more  ICCAD 1997»
13 years 11 months ago
Adaptive methods for netlist partitioning
An algorithm that remains in use at the core of many partitioning systems is the Kernighan-Lin algorithm and a variant the Fidducia-Matheysses (FM) algorithm. To understand the FM...
Wray L. Buntine, Lixin Su, A. Richard Newton, Andr...