Sciweavers

52 search results - page 8 / 11
» iccd 2005
Sort
View
ICCD
2005
IEEE
102views Hardware» more  ICCD 2005»
14 years 7 months ago
ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values
This paper proposes a response compactor, named ChiYun compactor, to compact scan-out responses in the presence of unknown values. By adding storage elements into an Xor network, ...
Mango Chia-Tso Chao, Seongmoon Wang, Srimat T. Cha...
ICCD
2005
IEEE
109views Hardware» more  ICCD 2005»
14 years 7 months ago
Optimizing the Thermal Behavior of Subarrayed Data Caches
Designing temperature-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density...
Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras
ICCD
2005
IEEE
111views Hardware» more  ICCD 2005»
14 years 7 months ago
Supply Voltage Degradation Aware Analytical Placement
Increasingly significant power/ground supply voltage degradation in nanometer VLSI designs leads to system performance degradation and even malfunction. Existing techniques focus...
Andrew B. Kahng, Bao Liu, Qinke Wang
ICCD
2005
IEEE
108views Hardware» more  ICCD 2005»
14 years 7 months ago
Methods for Modeling Resource Contention on Simultaneous Multithreading Processors
Simultaneous multithreading (SMT) seeks to improve the computation throughput of a processor core by sharing primary resources such as functional units, issue bandwidth, and cache...
Tipp Moseley, Dirk Grunwald, Joshua L. Kihm, Danie...
ICCD
2005
IEEE
110views Hardware» more  ICCD 2005»
14 years 7 months ago
Implementing Caches in a 3D Technology for High Performance Processors
3D integration is an emergent technology that has the potential to greatly increase device density while simultaneously providing faster on-chip communication. 3D fabrication invo...
Kiran Puttaswamy, Gabriel H. Loh