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ISCAS
2003
IEEE
126views Hardware» more  ISCAS 2003»
14 years 3 months ago
Bit rate optimized time-domain equalizers for DMT systems
The discrete multitone (DMT)transceivers have enjoyed great success in high speed data transmission. It is known that when the cyclicprefix is no shorterthan the channel impulse r...
Chun-Yang Chen, See-May Phoong
ISCAS
2003
IEEE
111views Hardware» more  ISCAS 2003»
14 years 3 months ago
A 2048 complex point FFT processor using a novel data scaling approach
In this paper, a novel data scaling method for pipelined FFT processors is proposed. By using data scaling, the'FFT processor can operateon a wide range of input signals with...
Thomas Lenart, Viktor Öwall
ISCAS
2003
IEEE
89views Hardware» more  ISCAS 2003»
14 years 3 months ago
Synthesizing checkers for on-line verification of System-on-Chip designs
In modern System-on-Chip (SoC) designs verification becomes the major bottleneck. Since by using state-of-theart techniques complete designs cannot be fully formally verified, it ...
Rolf Drechsler
ISCAS
2003
IEEE
169views Hardware» more  ISCAS 2003»
14 years 3 months ago
One class of transfer functions with monotonic step response
—The paper describes the transfer functions with monotonic step response. These functions required in design of wide-band pulse amplifiers were synthesized using the first semi-p...
Igor M. Filanovsky
ISCAS
2003
IEEE
96views Hardware» more  ISCAS 2003»
14 years 3 months ago
A novel improvement technique for high-level test synthesis
Improving testability during the early stages of High-Level Synthesis (HLS) has several benefits, including reduced test hardware overhead, reduced test costs, reduced design iter...
Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jaha...