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ISCAS
2006
IEEE
128views Hardware» more  ISCAS 2006»
14 years 1 months ago
Modeling and verification of high-speed wired links with Verilog-AMS
—Behavioral modeling with virtual built-in self-test verification of high-speed wired link designs is described in this paper. Our procedure is based on principles of top-down mi...
Ming-Ta Hsieh, Gerald E. Sobelman
ISCAS
2006
IEEE
77views Hardware» more  ISCAS 2006»
14 years 1 months ago
A parallel search algorithm for CLNS addition optimization
— We present analytical formulas for the calculation of the memory requirements for a system using the Complex Logarithmic Number System (CLNS). Certain properties of the CLNS ad...
Panagiotis D. Vouzis, Mark G. Arnold
ISCAS
2006
IEEE
105views Hardware» more  ISCAS 2006»
14 years 1 months ago
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs
This paper presents an approach to analyzing Edge Dummy and modeling of gated-oscillator (GO) -based CDRs and D.e.te...r G.t.. predicting their performance aspects such as jitter t...
Armin Tajalli, Paul Muller, Seyed Mojtaba Atarodi,...
ISCAS
2006
IEEE
110views Hardware» more  ISCAS 2006»
14 years 1 months ago
Network-on-chip link analysis under power and performance constraints
— This paper analyzes the behavior of interconnects in the highly structured environment of a network-on-chip (NoC). Two distinct classes of wires are considered, namely links be...
Manho Kim, Daewook Kim, Gerald E. Sobelman
ISCAS
2006
IEEE
112views Hardware» more  ISCAS 2006»
14 years 1 months ago
A CMOS potentiostat for control of integrated MEMS actuators
— We describe a potentiostat designed for in situ electrochemical control of MEMS actuators. This module is tailored for integration into a hybrid CMOS-MEMS system-ona-chip to co...
S. B. Prakash, Pamela Abshire, M. Urdaneta, M. Chr...