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ISCA
2006
IEEE
123views Hardware» more  ISCA 2006»
13 years 8 months ago
A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks
Packet-based on-chip networks are increasingly being adopted in complex System-on-Chip (SoC) designs supporting numerous homogeneous and heterogeneous functional blocks. These Net...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...
ISCA
2006
IEEE
131views Hardware» more  ISCA 2006»
14 years 2 months ago
Reducing Startup Time in Co-Designed Virtual Machines
A Co-Designed Virtual Machine allows designers to implement a processor via a combination of hardware and software. Dynamic binary translation converts code written for a conventi...
Shiliang Hu, James E. Smith
ISCAS
2006
IEEE
106views Hardware» more  ISCAS 2006»
14 years 2 months ago
Integrating observability don't cares in all-solution SAT solvers
— All-solution Boolean satisfiability (SAT) solvers are engines employed to find all the possible solutions to a SAT problem. Their applications are found throughout the EDA in...
Sean Safarpour, Andreas G. Veneris, Rolf Drechsler
ISCAS
2006
IEEE
96views Hardware» more  ISCAS 2006»
14 years 2 months ago
In-scale motion aligned temporal filtering
— To handle the mismatch problems of spatial-domain motion aligned temporal filtering (MATF) in providing spatial scalability, this paper presents a novel in-scale motion aligne...
Ruiqin Xiong, Jizheng Xu, Feng Wu, Shipeng Li
ISCAS
2006
IEEE
162views Hardware» more  ISCAS 2006»
14 years 2 months ago
Combined image signal processing for CMOS image sensors
This paper presents an efficient image signal processing structure for CMOS image sensors to achieve low area and power consumption. Although CMOS image sensors (CISs) have variou...
Kimo Kim, In-Cheol Park