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ISCAS
2006
IEEE
90views Hardware» more  ISCAS 2006»
14 years 2 months ago
Feature competition in a spike-based winner-take-all VLSI network
— Recurrent networks and hardware analogs that perform a winner-take-all computation have been studied extensively. This computation is rarely demonstrated in a spiking network o...
Shih-Chii Liu, Matthias Oster
ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
14 years 2 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
14 years 2 months ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
ISCA
2006
IEEE
107views Hardware» more  ISCA 2006»
14 years 2 months ago
Distributed Arithmetic on a Quantum Multicomputer
We evaluate the performance of quantum arithmetic algorithms run on a distributed quantum computer (a quantum multicomputer). We vary the node capacity and I/O capabilities, and t...
Rodney Van Meter, Kae Nemoto, W. J. Munro, Kohei M...
ISCA
2006
IEEE
114views Hardware» more  ISCA 2006»
14 years 2 months ago
Ensemble-level Power Management for Dense Blade Servers
One of the key challenges for high-density servers (e.g., blades) is the increased costs in addressing the power and heat density associated with compaction. Prior approaches have...
Parthasarathy Ranganathan, Phil Leech, David E. Ir...