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ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
Statistical timing analysis has been widely applied to predict the timing yield of VLSI circuits when process variations become significant. Existing statistical latch timing met...
ASPDAC
2006
ACM
14 years 2 months ago
2006
ACM
Symmetric input identification is an important technique in logic synthesis. Previous approaches deal with this problem by building BDDs and developing algorithms to determine symm...
ICCD
2006
IEEE
14 years 5 months ago
2006
IEEE
— This paper presents a framework for fast and accurate static timing analysis considering coupling. With technology scaling to smaller dimensions, the impact of coupling induced...
DATE
2006
IEEE
14 years 2 months ago
2006
IEEE
A concurrent core test approach is proposed to reduce the test cost of SOC. Multiple cores in SOC can be tested simultaneously by using a shared test set and scan chain disable. P...
ICCAD
2006
IEEE
14 years 2 months ago
2006
IEEE
In this paper, we propose a timing dependent dynamic power estimation framework that considers the impact of coupling and glitches. We show that relative switching activities and ...