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2006
IEEE
78views Hardware» more  DATE 2006»
14 years 4 months ago
STAX: statistical crosstalk target set compaction
This paper presents STAX, a crosstalk target set compaction framework to reduce the complexity of the crosstalk ATPG process by pruning non-fault-producing targets. In general, ex...
Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta,...
IOLTS
2006
IEEE
101views Hardware» more  IOLTS 2006»
14 years 4 months ago
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor
— Delay failures are becoming a dominant failure mechanism in nanometer technologies. Diagnosis of such failures is important to ensure yield and robustness of the design. Howeve...
Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury,...
IPPS
2006
IEEE
14 years 4 months ago
Placement and routing of Boolean functions in constrained FPGAs using a distributed genetic algorithm and local search
In this work we present a system for implementing the placement and routing stages in the FPGA cycle of design, into the physical design stage. We start with the ISCAS benchmarks,...
Manuel Rubio del Solar, Juan Manuel Sánchez...
VTS
2006
IEEE
93views Hardware» more  VTS 2006»
14 years 4 months ago
Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring
A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, ce...
Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram
ASPDAC
2006
ACM
105views Hardware» more  ASPDAC 2006»
14 years 4 months ago
Speed binning aware design methodology to improve profit under parameter variations
—Designing high-performance systems with high yield under parameter variations has raised serious design challenges in nanometer technologies. In this paper, we propose a profit-...
Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saib...