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ISLPED
2005
ACM
84views Hardware» more  ISLPED 2005»
14 years 3 months ago
Hierarchical power management with application to scheduling
This paper presented a hierarchical power management architecture which aims to facilitate power-awareness in an Energy-Managed Computer (EMC) system with multiple components. The...
Peng Rong, Massoud Pedram
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 3 months ago
Instruction packing: reducing power and delay of the dynamic scheduling logic
The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for...
Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghos...
ISLPED
2005
ACM
63views Hardware» more  ISLPED 2005»
14 years 3 months ago
Inter-program optimizations for conserving disk energy
Previous work has shown that intra-program optimizations, i.e., optimizations performed on individual programs in isolation, can be very effective in reducing disk energy in stre...
Jerry Hom, Ulrich Kremer
ISLPED
2005
ACM
68views Hardware» more  ISLPED 2005»
14 years 3 months ago
Low power SRAM techniques for handheld products
SRAM leakage constitutes a significant portion of the standby power budget of modern SoC products for handheld applications such as PDA and cellular phones. NMOS and PMOS reverse ...
Rabiul Islam, Adam Brand, Dave Lippincott
ISLPED
2005
ACM
101views Hardware» more  ISLPED 2005»
14 years 3 months ago
Energy-aware fetch mechanism: trace cache and BTB customization
1 A highly-efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing designs are inflexible and depending on pr...
Daniel Chaver, Miguel A. Rojas, Luis Piñuel...