Sciweavers

43 search results - page 6 / 9
» islped 2005
Sort
View
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 3 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
ISLPED
2005
ACM
110views Hardware» more  ISLPED 2005»
14 years 3 months ago
Complexity reduction in an nRERL microprocessor
We describe an adiabatic microprocessor implemented with a reversible logic, nRERL [1]. We employed an 8-phase clocked power instead of 6-phase one to reduce the number of buffers...
Seokkee Kim, Soo-Ik Chae
ISLPED
2005
ACM
111views Hardware» more  ISLPED 2005»
14 years 3 months ago
Peak temperature control and leakage reduction during binding in high level synthesis
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Mem...
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
14 years 3 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
ISLPED
2005
ACM
136views Hardware» more  ISLPED 2005»
14 years 3 months ago
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy
Concerns about the reliability of real-time embedded systems that employ dynamic voltage scaling has recently been highlighted [1,2,3], focusing on transient-fault-tolerance techn...
Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Ha...